EEPROMs are non-volatile memory devices which are erased and programmed using electrical signals. Within an EEPROM device are a plurality of memory cells, each of which may be individually programmed and erased. In general, each EEPROM cell has two transistors. As an example, a FLOTOX (floating gate-tunnel oxide) EEPROM cell includes a floating gate transistor and a select transistor. The select transistors in an EEPROM device are used to select individual EEPROM cells which are to be erased or programmed. The floating gate transistors in the device are those transistors which actually perform the erase and program operations in the individual cells. To program and erase a cell, a phenomenon known as Fowler-Nordheim tunneling is used to store either a positive or a negative charge, respectively, on a floating gate electrode of the floating gate transistor. Programming is accomplished by applying a positive voltage to a drain and a control gate of the select gate transistor while a control gate of the floating gate transistor is held at ground. As a result, electrons tunnel from the floating gate of the floating gate transistor through a tunnel dielectric to the drain, leaving the floating gate positively charged. An EEPROM cell is erased by storing negative charge on the floating gate. Negative charge storage on the floating gate is generally achieved by applying a positive voltage to the control gate of the transistor while grounding the drain and source. Such a bias causes electrons to tunnel from the channel regions through the tunnel dielectric to the floating gate, creating a negative charge on the floating gate.
One disadvantage of most EEPROM devices is that cell size is large, due to the fact that each cell has two transistors. In applications where circuit density is extremely important, an EEPROM cell may not be feasible. Another disadvantage is process complexity in that most EEPROM cells use two different gate oxide or dielectric thicknesses to achieve floating gate discharge. A thicker gate oxide is needed when applying a positive voltage to a drain of the select transistor during discharge, as compared to a thinner oxide which is needed to accomplish electron tunneling. The thicker gate oxide can reduce hot electron degradation induced from the high voltage applied on the drain. The applied high voltage also increases the spacing between the two transistors to reduce junction punch-through, making the EEPROM cell scaling harder.
An alternative to above mentioned EEPROM, is a flash EEPROM. Flash EEPROMs provide electrical erasing and programming capability, but generally have a increased circuit density since only one transistor per cell is needed. Several different structures have been demonstrated for use as flash EEPROMs, for example an ETOX (EPROM tunnel oxide) cell. Functionally, a flash EEPROM may be programmed by hot electron injection and erased via Fowler-Nordheim tunneling. Hot electron injection method is fast, typically taking about 10 .mu.s.
A disadvantage which might be made in performance if a flash EEPROM is used is a programming time delay caused by a problem known as "over-erase." In a flash EEPROM, erasing is accomplished by applying a bias to a source so that electrons stored in a floating gate tunnel to the source region. However in doing so, the floating gate often becomes positively charged, thereby lowering the threshold voltage (V.sub.T) of the channel region. Lower V.sub.T values correspond to weak hot electron generation, thus time involved in programming a memory cell is increased. Typically in programming a flash EEPROM cell, a control gate and a drain region are brought to a relatively high voltage, thereby creating an electric field at a junction of the channel region and drain and generating hot electrons at the junction. These electrons are then injected into the floating gate, thereby charging, or programming, the cell. If V.sub.T is low, the electric field which is created is weak, and electron generation at the junction is reduced. Thus, a lower V.sub.T implies a longer programming time. Another major problem of an over-erased cell is that it can act as a leakage source in a memory array. Such a leakage source can render an erroneous read of an adjacent cell.
One way to offset the longer programming time caused by the over-erase problem is to use a higher programming voltage. However, the trend in integrated circuits (ICs), especially those for portable electronic applications, is to reduce the power required to operate the chip. As the power supply voltage (V.sub.CC) is reduced, so to is the cell programming voltage, yet with low programming voltages the over-erase problem again emerges.
One solution to overcome read error caused by excessive leakage current from the over-erase problem is to add convergence or repairing to an over-erased bitcell. Repairing is a "low level" programming method and requires programming current and repairing time. For high density low voltage applications, where on-chip charge pumps are operated, programming current can be as high as amperes in block-erase. Yet, on-chip charge pumps have limited current sourcing capabilities. Thus, programming currents in cells with on-chip charge pumps are also limited, resulting in prolonged repair time caused by over-erase.
Therefore, a low voltage, low power, non-volatile memory cell which overcomes the problem of delayed programming times and delayed erased times without over-erase problem would be desirable. More specifically, it would be desirable for such a cell to have low program and erase currents, low program and erase voltages, yet sufficient read current for sensing the state of the cell. Moreover, it would be desirable for such a cell to be manufactured without significant process complexity and by a process which is compatible with existing metal-oxide-semiconductor (MOS) processing.